Project-V (FPGA Design)

Project-V (FPGA Design)

A 2D maze game on the DE1-SOC board developed in System Verilog. 


About.

  • Team size:  3 members
  • Duration: 3 weeks
  • Personal role: Programmer, Tester
  • Project role: Team leader 
  • Software: Altera Quartus 
  • Hardware: Altera DE1-SoC board
  • I/O support:
    • Input- Onboard switches and push-buttons.
    • Output- VGA port to screen (640x480 res.)
 

Project Outline.

  • Create an 2D maze game capable of outputing to the VGA port.
  • User can control their player object with the onboard push buttons and reset with associated switches
  • Onboard LEDs will provide visual feedback on which push button or switch is being pressed
  • SW[0] is defined as reset; terminating all VGA output and reject all input
  • SW[1] is defined as initialize; resetting the player object at it's starting position
 

Design Details.

VGA Output and Font Module Testing

Hurdles & Solutions.

Deciding to self develop a working VGA output model had yielded little success and pushed back many planned features that will be integrated into the code.

Solution: We found a working VGA module  from the Altera sit and a font module on Github. We quickly adapted both modules into our design, tested it, and transitioning focus to actually creating the game.

Resolution and Timing Adjustment

Hurdles & Solutions.

Different resolution output requires different VGA timing and porch variable sets. Hard coding one set of timing and porch set made test difficult on screen that only except certain resolutions.

Solution: We reference implementations by other VGA projects and created a header file sorting different set of timing and porch variables. Commenting out unneeded sets allowed us to change resolution reprogram the modules and save time on development. 

Maze Design Reference and User Input Testing

Hurdles & Solutions.

When we got to testing the user input and implementing the maze logic we had only four days left to complete the design.

Solution: Project was down scaled to not incorporate maze collider physics and we modeled an existing maze design into our maze output module. A push-button debounce module was programmed to address user input bug and final demo testing took place.

 

VGA main module

 

Player control and switch debounce module

 

VGA output module and param header

 

Map module 

 

Memo. 

  • Note: under such time constrained projects, it might be best practice to use existing open source code for basic project needs (input/output modules) and focus efforts into programming the features we really want to develop (maze physics). Our overambitious has gave us a deeper understand of development under System Verilog but also a downsized project.
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